mediaclock ? dtv, stb clock generat or cy2420 4 cypress semiconductor corporation 3901 north first street san jose , ca 95134 408-943-2600 document #: 38-07450 rev. *a revised september 8, 2003 features ? integrated phase-locked loop (pll) low jitter, high-accuracy outputs vcxo with analog adjust 3.3v operation benefits internal pll with up to 400mhz internal operation meets critical timing requirements in complex system designs large 150ppm range, better linearity enables application compatibility part number outputs input frequency output frequency range cy24204-1 3 27-mhz crystal input one copy of 27-mhz reference clock output, two copies of 27/27.027/74.250/74.175 mhz (frequency selectable) cy24204-2 4 27-mhz crystal input two copies of 27-mhz reference clock output, two copies of 27/27.027/74.250/74.175 mhz (frequency selectable) cy24204-3 4 27-mhz crystal input two copies of 27-mhz reference clock output, two copies of 27/27.027/74.250/74.17582418 mhz (frequency selectable) cy24204-4 4 27-mhz crystal input two copies of 27-mhz reference clock output, two copies of 27/27.027/74.250/74.17582418 mhz (frequency selectable, increased vcxo pull range) cy24204-5 4 27-mhz crystal input two copies of 27-mhz reference clock output, two copies of 27/27.027/74.250/74.17582418 mhz (frequency selectable, increased output drive strength) block diagram xin xout output multiplexer and dividers pll osc. clk1 q p vco vddl avss avdd vss fs0 fs1 clk2 refclk1 vssl vdd 16-pin tssop 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 vss vssl fs0 xin xout vdd vcxo avss refclk1 oe fs1 avdd vddl pin configurations nc clk2 oe vcxo clk1 16-pin tssop 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 vss vssl fs0 xin xout vdd vcxo avss refclk1 oe fs1 avdd vddl clk2 clk1 refclk2 24204-2,3,4,5 24204-1 refclk2 (-2,-3,-4,-5)
cy2420 4 document #: 38-07450 rev. *a page 2 of 6 frequency select options oe fs1 fs0 clk1/clk2 (-1,-2) [1] clk1/clk2 (-3,-4,-5) [1] refclk 1/2 unit 000 off off 27 mhz 001 off off 27 mhz 010 off off 27 mhz 011 off off 27 mhz 100 27 27 27 mhz 1 0 1 27.027 27.027 27 mhz 1 1 0 74.250 74.250 27 mhz 1 1 1 74.175 74.17582418 27 mhz pin description name pin number description xin 1 reference crystal input . v dd 2 voltage supply . av dd 3 analog voltage supply . vcxo 4 input analog control for vcxo . av ss 5 analog ground . v ssl 6 clk ground . n/c (-1) 7 no connect . refclk2 (-2,-3,-4,-5) 7 reference clock output . refclk1 8 reference clock output . clk1 (-1, -2) 9 27-/27.027-/74.250-/74.175-mhz clock output (frequency selectable) . clk1 (-3,-4,-5) 9 27-/27.027-/74.250-/74.17582418-mhz clock output (frequency selectable) . fs0 10 frequency select 0, weak internal pull-up . v ddl 11 clk voltage supply . clk2 (-1, -2) 12 27-/27.027-/74.250-/74.175-mhz clock output (frequency selectable) . clk2 (-3,-4,-5) 12 27-/27.027-/74.250-/74.17582418-mhz clock output (frequency selectable) . v ss 13 ground . fs1 14 frequency select 1 , weak internal pull-up. oe 15 output enable , weak internal pull-up. xout 16 reference crystal output . note: 1. ?off? = output is driven high.
cy2420 4 document #: 38-07450 rev. *a page 3 of 6 absolute maximum conditions supply voltage (v dd , av ddl , v ddl )..................?0.5 to +7.0v dc input voltage...................................... ?0.5v to v dd + 0.5 storage temperature (non-condensing) .... ?55 c to +125 c junction temperature ................................ ?40 c to +125 c data retention @ tj=125 c..................................> 10 years package power dissipation...................................... 350 mw esd (human body model) mil-std-883.................... 2000v (above which the useful life may be impaired. for user guide- lines, not tested.) pullable crystal specifications parameter description comments min. typ. max. unit f nom nominal crystal frequency parallel resonance, fundamental mode, at cut 27.0 mhz c lnom nominal load capacitance 14 pf r 1 equivalent series resistance (esr) fundamental mode 25 ? r 3 /r 1 ratio of third overtone mode esr to fundamental mode esr ratio used because typical r 1 values are much less than the maximum spec 3 dl crystal drive level no external series resistor assumed 0.5 2 mw f 3sephi third overtone separation from 3*f nom high side 300 ppm f 3seplo third overtone separation from 3*f nom low side ?150 ppm c 0 crystal shunt capacitance 7pf c 0 /c 1 ratio of shunt to motional capacitance 180 250 c 1 crystal motional capacitance 14.4 18 21.6 ff recommended operating conditions parameter description min. typ. max. unit v dd /av ddl /v ddl operating voltage 3.135 3.3 3.465 v t a ambient temperature 0 70 c c load max. load capacitance 15 pf t pu power-up time for all v dd ?s to reach minimum specified voltage (power ramps must be monotonic) 0.05 500 ms dc electrical specifications parameter [2] name description min. typ. max. unit i oh1 output high current for -1,-2,-3,-4 v oh = v dd ? 0.5, v dd /v ddl = 3.3v 12 24 ma i ol1 output low current for -1,-2,-3,-4 v ol = 0.5, v dd /v ddl = 3.3v 12 24 ma i oh2 output high current for -5 v oh = v dd ? 0.5, v dd /v ddl = 3.3v 18 26 ma i ol2 output low current for -5 v ol = 0.5, v dd /v ddl = 3.3v 18 26 ma v ih input high voltage cmos levels, 70% of v dd 0.7 v dd v il input low voltage cmos levels, 30% of v dd 0.3 v dd i vdd supply current av dd /v dd current 25 ma i vddl supply current v ddl current (v ddl = 3.47v) 20 ma c in input capacitance 7pf f ? xo v cxo pullability range nominal pullability for -1,-2,-3,-5 150 ppm f ? xo v cxo pullability range extended pullability for -4 200 ppm v vcxo v cxo input range 0 v dd v r up pull-up resistor on inputs v dd = 3.14 to 3.47v, measured at v in = 0v 100 150 k ? note: 2. not 100% tested.
cy2420 4 document #: 38-07450 rev. *a page 4 of 6 test and measurement set-up voltage and timing definitions ac electrical specifications parameter [2] name description min. typ. max. unit dc output duty cycle duty cycle is defined in figure 1 ; t1/t2, 50% of v dd 45 50 55 % er 1 rising edge rate for -1,-2,-3,-4 output clock edge rate, measured from 20% to 80% of v dd , c load = 15 pf see figure 2 . 0.8 1.4 v/ns ef 1 falling edge rate for -1,-2,-3,-4 output clock edge rate, measured from 80% to 20% of v dd , c load = 15 pf see figure 2 . 0.8 1.4 v/ns er 2 rising edge rate for -5 output clock edge rate, measured from 20% to 80% of v dd , c load = 15 pf see figure 2 . 1.0 1.8 v/ns ef 2 falling edge rate for -5 output clock edge rate, measured from 80% to 20% of v dd , c load = 15 pf see figure 2 . 1.0 1.8 v/ns t 9 clock jitter clk1, clk2 peak-peak period jitter 120 ps t 10 pll lock time 3ms 0.1 f v dds outputs c load gnd dut clock output v dd 50% of v dd 0v t 1 t 2 figure 1. duty cycle definition clock output t 3 t 4 v dd 80% of v dd 20% of v dd 0v figure 2. er = (0.6 x v dd ) /t3, ef = (0.6 x v dd ) /t4
cy2420 4 document #: 38-07450 rev. *a page 5 of 6 ? cypress semiconductor corporation, 2003. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semi conductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support syst ems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies th at the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. package drawing and dimensions mediaclock is a trademark of cypress semiconductor. all product and company names mentioned in this document may be the trademarks of their respective holders. ordering information ordering code package name package type operating range operating voltage cy24204zc-1 z16 16-pin tssop commercial 3.3v CY24204ZC-1T z16 16-pin tssop commercial 3.3v cy24204zc-2 z16 16-pin tssop commercial 3.3v cy24204zc-2t z16 16-pin tssop commercial 3.3v cy24204zc-3 z16 16-pin tssop commercial 3.3v cy24204zc-3t z16 16-pin tssop commercial 3.3v cy24204zc-4 z16 16-pin tssop commercial 3.3v cy24204zc-4t z16 16-pin tssop commercial 3.3v cy24204zc-5 z16 16-pin tssop commercial 3.3v cy24204zc-5t z16 16-pin tssop commercial 3.3v 16-lead thin shrunk small outline package (4.40 mm body) z16 51-85091-**
cy2420 4 document #: 38-07450 rev. *a page 6 of 6 document history page document title: cy24204 mediaclock? dtv, stb clock generator document number: 38-07450 rev. ecn no. issue date orig. of change description of change ** 123842 04/10/03 ckn new data sheet *a 128775 09/0803 ija added -4 and -5 parts
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